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Communicating Process Architectures

The CPA 2011 proceedings are available from IOS Press; in addition, all papers and presentations from the conference can be found in the WoTUG paper database.

We are currently planning CPA 2012 — watch this space!

About WoTUG

WoTUG provides a forum for the discussion and promotion of concurrency ideas, tools and products in computer science. It organises specialist workshops and annual conferences that address key concurrency issues at all levels of software and hardware granularity. WoTUG aims to progress the leading state of the art in:

theory (programming models, process algebra, semantics, ...);

practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);

education (at school, undergraduate and postgraduate levels, ...);

applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);

for the next generation of scalable computer infrastructure (hard and soft) and application, where scaling means the ability to ramp up functionality (stay in control as complexity increases) as well as physical metrics (such as absolute performance and response times);

for system integrity (dependability, security, safety, liveness, ...);

for making things simple.

WoTUG publications

A database of papers and presentations from WoTUG conferences is here. The Abstract below has been randomly selected from this database.

Synchronisation in a Multithreaded Processor

A multithreaded architecture exploits instruction level parallelism by interleaving instructions from disjoint thread contexts. As each thread executes within its own instruction stream with private data (the context registers), there is no interdependency between instructions from different threads. This allows high resource utilisation of a super scalar pipelined processor at a very low cost, in terms of complexity and silicon area. A new synchronisation mechanism for a multithreaded architecture is outlined. Two new instructions have been introduced to perform one to one and n-way synchronisation. The operation allows synchronisations to be requested and actioned efficiently on chip in as little as four clock cycles. Barriers and CSP style channels can easily be constructed with this new synchronisation instruction. A brief examination of performance of this multithreaded architecture shows that the optimum number of contexts per multithreaded processing element is four, based on test programs.