@InProceedings{Wiggers05, title = "{A}rchitecture {D}esign {S}pace {E}xploration for {S}treaming {A}pplications through {T}iming {A}nalysis", author= "Wiggers, Maarten H. and Kavaldjiev, Nikolay and Smit, Gerard J. M. and Jansen, Pierre G.", editor= "Broenink, Jan F. and Roebbers, Herman and Sunter, Johan P. E. and Welch, Peter H. and Wood, David C.", pages = "219--233", booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2005", isbn= "978-1-58603-561-7", year= "2005", month= "sep", abstract= "In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application\&\#8217;s throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations." }