@InProceedings{SaifhashemiBeerel05,
  title =        "{H}igh {L}evel {M}odeling of {C}hannel-{B}ased {A}synchronous {C}ircuits {U}sing {V}erilog",
  author=        "Saifhashemi,  Arash and Beerel,  Peter A.",
  editor=        "Broenink,  Jan F. and Roebbers,  Herman and Sunter,  Johan P. E. and Welch, Peter H. and Wood,  David C.",
  pages =        "275--288",
  booktitle=     "{C}ommunicating {P}rocess {A}rchitectures 2005",
  isbn=          "978-1-58603-561-7",
  year=          "2005",
  month=         "sep",
  abstract=      "In this paper we describe a method for modeling
     channel-based asynchronous circuits using Verilog HDL. We
     suggest a method to model CSP-like channels in Verilog HDL.
     This method also describes nonlinear pipelines and high
     level channel timing properties, such as forward and
     backward latencies, minimum cycle time, and slack. Using
     Verilog enables us to describe the circuit at many levels of
     abstraction and to use the commercially available CAD tools."
}