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db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"<br>

%T High Level Modeling of Channel\-Based Asynchronous Circuits Using Verilog
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%A  Arash Saifhashemi,  Peter A. Beerel
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%E  Jan F. Broenink,  Herman Roebbers,  Johan P. E. Sunter, Peter H. Welch,  David C. Wood
%B Communicating Process Architectures 2005
%X In this paper we describe a method for modeling
   channel\-based asynchronous circuits using Verilog HDL. We
   suggest a method to model CSP\-like channels in Verilog HDL.
   This method also describes nonlinear pipelines and high
   level channel timing properties, such as forward and
   backward latencies, minimum cycle time, and slack. Using
   Verilog enables us to describe the circuit at many levels of
   abstraction and to use the commercially available CAD tools.