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%T An Evaluation of Intel\[rs]s Restricted Transactional Memory for CPAs
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%A  Carl G. Ritson,  Frederick R. M. Barnes
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%E Peter H. Welch,  Frederick R. M. Barnes,  Jan F. Broenink,  Kevin Chalmers,  Jan Bækgaard Pedersen,  Adam T. Sampson
%B Communicating Process Architectures 2013
%X With the release of their latest processor
   microarchitecture,
codenamed Haswell, Intel added new
   Transactional Synchronization
Extensions (TSX) to their
   processors\[rs] instruction set. These
extensions include
   support for Restricted Transactional Memory (RTM),
a
   programming model in which arbitrary sized units of memory
   can be
read and written in an atomic manner. This paper
   describes the
low\-level RTM programming model, benchmarks
   the performance of its
instructions and speculates on how it
   may be used to implement and
enhance Communicating Process
   Architectures.