From: hjstein@bfr.co.il (Harvey J. Stein)
Newsgroups: comp.lang.fortran,comp.parallel.pvm
Subject: Re: fortran77 programming
Date: 07 Dec 1998 11:01:32 +0200
Organization: Unspecified Organization
Message-Id: <m2lnkkba1f.fsf@blinky.bfr.co.il>
References: <3660D892.E1EDBF12@est.it> <3665044D.A0F57E59@kings.uq.edu.au>
    <3665E491.7993355@flash.net> <y6k909mqww.fsf@tweedledumb.cygnus.com>
    <m21zmgnuau.fsf@blinky.bfr.co.il> <y6emqejtgq.fsf@tweedledumb.cygnus.com>
    <m2d85xi988.fsf@blinky.bfr.co.il> <y6yaokiw0r.fsf@tweedledumb.cygnus.com>
Cc: hjstein@bfr.co.il
Xref: ukc comp.lang.fortran:61896 comp.parallel.pvm:7845


Craig Burley <burley@tweedledumb.cygnus.com> writes:

 > hjstein@bfr.co.il (Harvey J. Stein) writes:
 >
 > Doesn't matter.  You won't get superlinear speedups by using parallel
 > hardware.  I don't care whether your application is real-time or not.

I came into the middle of this when I saw your post on
comp.parallel.pvm.  It seems I might have missed the point that it's a
long discussion about superlinear speedups in multi-cpu boxes.

In any case, I can't really abide by your "all else being equal"
assumptions, because when talking about multi-cpu SMP boxes, one
typically means N CPUs in 1 box with appropriate support hardware vs 1
of the same CPUs in 1 box with appropriate support hardware.  One also
typically requires the same OS, etc on each system.  This rules out
things like letting the single cpu system have the same amt of total
cache & same total # of registers as the N CPU box.

Under these conditions I just wanted to point out that one could
imagine the N CPU box giving better performance than the single CPU
box (containing a CPU running N times faster) because there could be
fewer context switches with the single CPU box.  Of course, I'd expect
that the difference in performance would be close to unmeasurable
because I'd expect the context switch overhead to be extremely small,
but it should still be there.

-- 
Harvey J. Stein
BFM Financial Research
hjstein@bfr.co.il

