Newsgroups: comp.sys.transputer
From: Jonathan Bromley <jseb@oxim.demon.co.uk>
Subject: Re: Short memories
Organization: Oxford Intelligent Machines Ltd
Date: Tue, 25 Nov 1997 14:33:24 +0000
Mime-Version: 1.0
Message-ID: <k5HYKAA0Gue0UAvM@oxim.demon.co.uk>

In article <879816492snz@nlcc.demon.co.uk>, Mark Ian Barlow
<Mark@nlcc.demon.co.uk> writes
>snip>
>It also occurred to me that Psion have a quite commendable OS for
>the StrongARM, which they're trying to license into other embedded
>application areas (portable telecom, STBs &c.) at present
yes Mark, but it is not pre-emptive (at least, the x86 version
of Epoc wasn't; sorry if I'm out of date) and although it is very
nicely engineered it was definitely designed as an operating system
and so its threads are a bit heavyweight - they carry loads of
OS baggage around with them, memory management stuff, file handles, 
all the usual second-year operating systems course stuff - and 
would not be a good match for Transputerish PAR things.

Indeed, in this discussion of why-can't-we-have-a-surrogate-Transputer
there has been remarkably little mention of the Transputer's most
mind-blowing feature, the support for multi-threading in microcode;
recall that it was based not only on a formal paradigm (CSP) but also
a very clear-headed implementation model, with the machine itself
knowing about descheduling points and so on.  Very hard to emulate
efficiently using any machine that doesn't already know about such
things. A really efficient ALT in software is quite a challenge.

IMHO the Transputer Link is somewhat overrated.  It's only there to
provide a physical realisation of channel I/O and it is done in a 
fairly naive way; in particular it is VERY difficult to make the 
Link communications robust against soft errors.  Re-engineering
the Link could be a useful spinoff from any of these proposals.
(Sorry, Mark knows I've been banging on about the fragility of 
Links for years, but I thought I'd say it again anyhow).

Has anyone asked the hardware compilation folk at Oxford Univ. or at
Embedded Solutions Ltd whether they have tried to write a Transputer
CPU in a hardware description language so that it would fit on a big
FPGA?  Now there's a REALLY nice project that could even keep
soldering-iron merchants like me happy for a while..... and you could
make Savile Row transputers.... eight links, sir? of course, just allow
me to change this iterator....  All the RAM would have to go off chip,
but with 20ns SRAM at about $60/megabyte even in small quantity, we 
could have lots of fun. And we wouldn't need a volume customer to get
started.

Jonathan Bromley
not necessarily speaking for
Oxford Intelligent Machines Ltd