Paper Details

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Hardware/Software Synthesis and Verification Using Esterel

Authors: db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
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Singh, Satnam

Abstract:

The principal contribution of this paper is the demonstration of a promising technique for the synthesis of hardware and software from a single specification which is also amenable to formal analysis. We also demonstrate how the notion of synchronous observers may provide a way for engineers to express formal assertions about circuits which may be more accessible then the emerging grammar based approaches. We also report that the semantic basis for the system we evaluate pays dividends when formal static analysis is performed using model checking.

Proceedings:

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Communicating Process Architectures 2007, db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
Alistair A. McEwan, Steve Schneider, Wilson Ifill, Peter H. Welch, 2007, pp 371 - 378 db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"
published by IOS Press, Amsterdam

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db_connect: Could not connect to paper db at "wotug@dragon.kent.ac.uk"

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