Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2017,
the 39th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 20th. to Wednesday August 23rd. 2017 and is hosted by
Kevin Vella, Head of Department in
at the University of Malta.
Conference sessions will take place at the
Victoria Hotel in Sliema, Malta.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Design of a Transputer Core and Implementation in an FPGA
We have made an IP (Intellectual Property) core for the T425 transputer. The same machine instructions as the transputer are executable in this IP core (we call it TPCORE). To create an IP code for the transputer has two aspects. On one hand, if we could succeed in building our own one and put it in an FPGA, we could apply it as a core processor in a distributed system. We also intend to put it in a VLSI chip. On the other hand, if we can extend our transputer development starting from a very conventional one to more sophisticated ones, as Inmos proceeded to the T9000, we will eventually find our technological breakthrough for the bottlenecks that the original transputer had, such as the restriction of the number of communication channels. It is important to have an IP core for the transputer. Although TPCORE uses the same register set with the same functionality as transputer and follows the same mechanisms for link communication between two processes and interrupt handling, the implementation must be very different from original transputer. We have extensively used the micro-code ROM to describe any states that TPCORE must take. Using this micro code ROM for the state transition description, we could implement TPCORE economically on FPGA space and achieve efficient performance.