Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2016,
the 38th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 21st. to Wednesday August 24th. 2016 and is hosted by the
Niels Bohr Institute,
University of Copenhagen.
Conference sessions will take place at the
Hans Christian Ørsted Institute, which is located
The evening Fringe sessions will be at the
which is just
a few minutes walk from the Ørsted buildings.
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
and to stimulate discussion and ideas on the roles concurrency will play in the future:
theory (programming models, process algebra, semantics, ...);
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
education (at school, undergraduate and postgraduate levels, ...);
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
Of course, neither of the above sets of bullets are exclusive.
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
for system integrity (dependability, security, safety, liveness, ...);
for making things simple.
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
A Comparison Of Data-Parallel Programming Systems With Accelerator
Data parallel programming provides an accessible model for exploiting
the power of parallel computing elements without resorting to the
explicit use of low level programming techniques based on locks,
threads and monitors.
The emergence of GPUs with hundreds or thousands of processing
cores has made data parallel computing available to a wider class of
programmers. GPUs can be used not only for accelerating the
processing of computer graphics but also for general purpose
data-parallel programming. Low level data-parallel programming
languages based on the CUDA provide an approach for developing
programs for GPUs but these languages require explicit creation and
coordination of threads and careful data layout and movement. This has
created a demand for higher level programming languages and libraries
which raise the abstraction level of data-parallel programming and
increase programmer productivity.
The Accelerator system was developed by Microsoft for writing data
parallel code in a high level manner which can execute on GPUs,
multicore processors using SSE3 vector instructions and FPGA chips.
This paper compares the performance and development effort of
the high level Accelerator system against lower level systems which are
more difficult to use but may yield better results. Specifically,
we compare against the NVIDIA CUDA compiler and sequential C++
code considering both the level of abstraction in the
implementation code and the execution models. We compare the
performance of these systems using several case studies. For some
classes of problems, Accelerator has a performance comparable to
CUDA, but for others its performance is significantly reduced
however in all cases it provides a model which is easier to use and
allows for greater programmer productivity.