Paper Details

An Evaluation of Intel's Restricted Transactional Memory for CPAs

Authors: Ritson, Carl G., Barnes, Frederick R. M.

Abstract:

With the release of their latest processor microarchitecture, codenamed Haswell, Intel added new Transactional Synchronization Extensions (TSX) to their processors' instruction set. These extensions include support for Restricted Transactional Memory (RTM), a programming model in which arbitrary sized units of memory can be read and written in an atomic manner. This paper describes the low-level RTM programming model, benchmarks the performance of its instructions and speculates on how it may be used to implement and enhance Communicating Process Architectures.

Proceedings:

Communicating Process Architectures 2013, Peter H. Welch, Frederick R. M. Barnes, Jan F. Broenink, Kevin Chalmers, Jan Bækgaard Pedersen, Adam T. Sampson, 2013, pp 271 - 292 published by Open Channel Publishing Ltd., Bicester

Files: Paper (PDF), Slides (PDF)

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