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@InProceedings{Teig98,
  title = "{PAR} and {STARTP} {T}ake the {T}anks",
  author= "Teig, Øyvind",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "1--18",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "The article describes how SPoC (Southampton Portable occam
     Compiler) has been used -- together with hand-written C --
     in Autronica's new GL-100 radar-based fluid gauge. The final
     C-code is running on a Texas TMS320C32 DSP. Some 2600 lines
     of C code have been automatically translated from the occam
     sources. SPoC's non-preemptive scheduling filled our needs
     with a few exceptions. The main problem has been aligning
     occam 2 and ANSI-C data abstractions. A realtime system
     based on language support of high-level concurrency
     abstractions (as opposed to separate real-time kernel and
     use of library calls without direct language support) is
     soon to monitor worldwide charging and discharging of oil
     tankers."
}
@InProceedings{CoxNicole98,
  title = "{C}ommodity {H}igh {P}erformance {C}omputing at {C}ommodity {P}rices",
  author= "Cox, Simon J. and Nicole, Denis A. and Takeda, Kenji",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "19--26",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "The entry price of supercomputing has traditionally been
     very high. As processing elements, operating systems, and
     switch technology become cheap commodity parts, building a
     powerful supercomputer at a fraction of the price of a
     proprietrary system becomes realistic. We have recently
     purchased, in support of both our local and national
     collaborations, a dedicated computational cluster of eight
     DEC Alpha workstations. Each node has a 500MHz AXP 21164A
     processor with 256Mb memory running Windows NT 4.0 and cost
     under 6000 pounds. They are connected by 100Mb/s switched
     ethernet. In this paper we discuss some of the issues raised
     by our choice of processor, operating system and
     interconnection network. The results we present indicate
     that the cluster is fully competitive with systems from
     major vendors for a wide range of engineering and science
     applications, and at a lower cost by at least a factor of
     three. Indeed the only current area of under-performance
     relative to these vendors' high-end offerings is the
     inter-node network bandwidth and latency. We give some
     initial results indicating how the network performance might
     be improved under Windows NT."
}
@InProceedings{GreveSchwirtz98,
  title = "{A}n {A}/{D} {D}/{A} board using {IEEE}-1355 {DS}-{L}inks for {H}eterogeneous {M}ultiprocessor {E}nvironment",
  author= "Greve, O. J. and Schwirtz, M. H. and Hilderink, Gerald H. and Broenink, Jan F. and Bakkers, Andr\`{e} W. P.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "27--38",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "In our approach for developing heterogeneous control
     systems, we have developed a real-time A/D D/A board called
     \"the Raptor\". The Raptor communicates over
     high-speed and highly-reliable DS-links (IEEE-1355). To
     obtain highly accurate analogue conversions, the A/D and D/A
     converteds have a 12-bit resolution. We measured a maximum
     sampling frequency of 90.5kHz on each A/D channel. The
     maximum sampling frequency of each D/A channel has been
     measured to be approximately 145kHz. For communication with
     the rest of the control environment, two 100Mbit/s DS-links
     are available. A data transfer rate of 5.57Mbytes/s has been
     achieved on each DS-link adapter. The Raptor forms a part of
     a heterogeneous multiprocessor closed-loop control
     environment. This new environment can be used, amongst
     others, for controlling heavy robot applications. The work
     on this environment takes place in scope of JavaPP (Java
     Plug and Play) project. The software will be developed
     together with the CJT-library that provides inherent
     object-orientated and parallel design patterns, according to
     CSP paradigm, in Java."
}
@InProceedings{ONeillCoulson98,
  title = "{A} {D}istributed {P}arallel {P}rocessing {S}ystem for the {S}trong{ARM} {M}icroprocessor",
  author= "O'Neill, Brian C. and Coulson, G. C. and Wong, Adam K. L. and Hotchkiss, R. and Ng, J. H. and Clark, S. and Thomas, P. D. and Cawley, A.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "39--48",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "Recent developments in hardware message routing devices have
     demonstrated significant performance benefits for parallel
     processing networks. This work describes a system which uses
     a single chip interface between the high performance
     StrongARM processor and the existing ICR C416 message
     routing chip. The ICR C416 is a non-blocking communications
     routing device. Each device allows concurrent communications
     with up to 16 processors. A distributed parallel processing
     system can be constructed using the StrongARM and ICRC416
     devices, with features similar to that of a transputer
     system but with the benefits of the higher clock speed and
     cache memory of the StrongARM processor."
}
@InProceedings{BoostenDobinson98,
  title = "{A} {PCI}-based {N}etwork {I}nterface {C}ontroller for {IEEE} 1355 {DS}-{L}inks",
  author= "Boosten, Marcel and Dobinson, R. W. and Martin, B. and Stok, P. D. V. van der",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "49--68",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "We have investigated the construction of a parallel computer
     using IEEE 1355 high-throughput low-latency DS link networks
     and high-performance commodity processors running a standard
     operating system. In this context a DS Network Interface
     Controller (DSNIC) has been developed. The board's hardware,
     controlled by FPGA firmware, together with the host
     software, provides a CSP based message passing interface
     between standard OS processes. This paper describes how the
     design and realisation of the DSNIC refleat our aim:
     low-latency high-throughput inter-process communication. We
     show the benchmark results, their analysis, and suggest
     further performance gains that might be possible."
}
@InProceedings{AndersonBoosten98,
  title = "{IEEE} 1355 {DS}-{L}inks: {P}resent {S}tatus and {F}uture {P}rospects",
  author= "Anderson, C. R. and Boosten, Marcel and Dobinson, R. W. and Haas, S. and Heeley, R. and Madsen, N. A. H. and Martin, B. and Pech, J. and Thornley, D. A. and Ullod, C. L.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "69--80",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "IEEE 1355 HS-Links and their support devices have been
     investigated as part of the ESPRIT projects Macram\`{e} and
     Arches. A description of the HS-Link technology and initial
     experience with the RCube 8-way packet router and the Bullit
     HS-Link interface device are presented. A 64 node HS-Link
     switching network based using these devices is being
     constructed at CERN. We report on the design and
     construction of the network testbed."
}
@InProceedings{AuburyPage98,
  title = "{A}dvanced {S}ilicon {P}rototyping in a {R}econfigurable {E}nvironment",
  author= "Aubury, Matt and Page, Ian and Plunkett, Dominic and Sauer, Matthias and Saul, Jonathan",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "81--92",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "A flow is proposed which offers a programming approach to
     the systems design of application specific
     micro-controllers. This flow is based on Handel-C, an
     occam-based language with C-like syntax for hardware
     compilation. Tools have been developed for compilation and
     concurrent simulation (co-simulation) of hardware and
     software parts of a system, and a reconfigurable board has
     been designed which can be used for rapid prototyping of the
     application specific micro-controller. The final design can
     be compiled into a structural VHDL netlist for a standard
     cell ASIC process."
}
@InProceedings{MartinJassim98,
  title = "{A} {T}echnique for {C}hecking the {CSP} sat {P}roperty",
  author= "Martin, Jeremy M. R. and Jassim, S. A.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "93--110",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "This paper presents an algorithm for checking that a CSP
     process satisfies a specification defined by a
     boolean-valued function on its traces and refusals, i.e. P
     sat f(tr, ref) This is contrasted with the refinement
     approach, as implemented by the FDR tool, of checking that
     one CSP process is a possible implementation of another,
     i.e. P \>= SPEC"
}
@InProceedings{Lawrence98a,
  title = "{E}xtending {CSP}",
  author= "Lawrence, Adrian E.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "111--132",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "CSP, timed or untimed, has not included a general treatment
     of priority, although the PRI ALT constructor is an
     essential part of occam. This paper introduces CSPP which
     includes a generalization of PRI ALT in the form of a
     prioritized external choice P \<pribox\> Q. PRI PAR is
     also included. A new denotational semantics is introduced,
     although only the simplest model is outlined. The work is
     intended to provide a solid rogorous foundation for
     hardware-software codesign. And a companion paper describes
     untimed HCSP which is a further extension of CSP built upon
     these foundations. It was first presented informally at the
     Twente WoTUG-20 technical meeting."
}
@InProceedings{Lawrence98b,
  title = "{HCSP}: {E}xtending {CSP} for {C}odesign and {S}hared {M}emory",
  author= "Lawrence, Adrian E.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "133--156",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "HCSP is a variant of CSP adapted to capture the semantics of
     hardware compilation, among other purposes. It extends CSP
     in several ways; it includes priority; events can be
     combined; new synchronization constructors are introduced;
     and state is explicitly modelled. Including state permits
     the treatment of shared memory as well as message passing
     systems. A possible denotational semantics is included here
     ths allowing proper treatment of such systems. Although most
     of these extensions were motivated by the needs of hardware
     compilation, HCSP can be applied more widely including
     software and thus can form the foundation of a codesign
     language. HCSP is an extension of CSPP; familiarity of CSPP
     is assumed here."
}
@InProceedings{Kalogerop98,
  title = "{D}eveloping an optimising compiler for occam",
  author= "Kalogeropoulos, Spiridon",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "157--166",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "occam is a high-level language which got constructs for
     generating explicitly concurrent processes which communicate
     using channels. In this paper we present our methodology for
     developing an optimising occam compiler which consist of a
     framework to represent concurrency and the semantic
     properties of an occam program that enables efficient
     process optimisations, and inter-procedural optimisations to
     be performed. Furthermore, we tackle the issue of
     retargeting the optimising occam compiler for different
     processors of the transputer family."
}
@InProceedings{SheenAllen98,
  title = "oc-{X}: an {O}ptimising {M}ultiprocessor occam {S}ystem for the {P}ower{PC}",
  author= "Sheen, Tim and Allen, Alastair R. and Ripke, Andreas and Woo, Stacy",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "167--186",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "The development of a PowerPC port of the KRoC (portable
     occam compiler) is described. As well as the basic port, a
     multiprocessor run time system provides services for user
     programs, including efficient occam channels between
     distributed processes, natural access to host file systems
     and TCP/IP network sockets. Optimization of target assembly
     code is discussed, with methods for removing the
     inefficiencies introduced by the KRoC translation process."
}
@InProceedings{Poole98,
  title = "{E}xtended {T}ransputer {C}ode -- a {T}arget-{I}ndependent {R}epresentation of {P}arallel {P}rograms",
  author= "Poole, Michael D.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "187--198",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "The transputer instruction set and its symbolic
     representation are reviewed. An alternative representation
     named ETC-code, suitable for an intermediate representation
     in a retargettable occam compiler, is motivated and
     described. The translation of such a language into a variety
     of alternative target languages is discussed. Its use as a
     representation for programs whose target processor type is
     not yet known is proposed."
}
@InProceedings{WongLau98,
  title = "{MALT}: {A} {M}ultiway {A}lternation {C}onstruct for occam",
  author= "Wong, Adam K. L. and Lau, Francis C. M.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "199--210",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "The alternation construct in occam provides a form of binary
     selective communication to the cooperating tasks of a
     concurrent computation. The use of this construct could lead
     to increased responsiveness and efficiency of concurrent
     programs. However, the expressiveness of the construct is
     restricted in the sense that only two parties can be
     involved in a communication. We extend the current
     implementation of the alternation construct to accept an
     arbitrary number of channel inputs such that multiway (as
     opposed to binary) selective communication is made possible.
     A new construct called multiway alternation --
     \"MALT\", is proposed for occam and is implemented
     in the transputer hardware."
}
@InProceedings{Umland98,
  title = "{P}arallel {G}raph {C}olouring using {J}ava",
  author= "Umland, Thomas",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "211--218",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "In this paper a parallel, pipeline orientated version of a
     well-known sequential graph coloring heuristic is
     introduced. Runtime and speedup results of an implementation
     in JAVA on a four processor machine are presented and
     discussed."
}
@InProceedings{Sousa CasJr98,
  title = "{A} {F}ault-{T}olerant {O}n-board {C}omputer for {S}pace {A}pplications",
  author= "Sousa Castro, Helano de and Jr, Jo\~{a}o Reinaldo Imbiriba and Silveira, Jarbas Aryel N. and Santiago, Valdivino and Monteiro, Ant\^{o}nio Miguel Vieira",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "219--230",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "The first Brazilian microsatellite will be launched at the
     middle of 1998. The on-board computer, named Trisputer, will
     play a major part in the mission, since it will perform
     essential on-board functions, such, as guidance, control of
     the on-board instrumentation, telemetry/telecommand, and
     control of some on-board scientific experiments. The
     Trisputer is a fault-tolerant multiprocessor computer with a
     high reliability, when compared to such systems as TMR, and
     Duplex. This paper describes the conception and
     implementation of the hardware of this computer, as well as
     it shows its reliability model."
}
@InProceedings{KatalovKatalov98,
  title = "{D}esign and {M}onitoring {S}ystems for {P}arallel {P}rogramming",
  author= "Katalov, Alexander J. and Katalov, Vladimir J. and Nikolaev, Vladimir K.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "231--258",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
  abstract= "In this paper we consider computer-based systems for
     designing, debugging, tuning and optimising parallel
     programs. The development of such systems is complicated and
     labour-intensive. Despite this, many interesting projects
     have been developed in the last few years, which can be
     effectively used to design and debug programs for parallel
     architectures. We analyse the current state in this area and
     the various approaches are compared."
}
@InProceedings{Welch98,
  title = "{J}ava {T}hreads in the light of occam/{CSP}",
  author= "Welch, Peter H.",
  editor= "Welch, Peter H. and Bakkers, Andr\`{e} W. P.",
  pages = "259--284",
  booktitle= "{P}roceedings of {W}o{TUG}-21: {A}rchitectures, {L}anguages and {P}atterns for {P}arallel and {D}istributed {A}pplications",
  isbn= "90 5199 391 9",
  year= "1998",
  month= "mar",
}

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