WoTUG - The place for concurrent processes

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@InProceedings{Cole12b,
  title = "{H}andel-{C}++ - {A}dding {S}yntactic {S}upport to {C}++",
  author= "Cole, Alex",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{Li12,
  title = "{I}mplementation of an {A}gent-based {M}odel with {TBB} {T}echnique",
  author= "Li, Ye",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{Welch12b,
  title = "{U}nfinished {B}usiness - occam-pi²",
  author= "Welch, Peter H.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{BarrocasOliveira12b,
  title = "{JC}ircus {D}emo",
  author= "Barrocas, S.L.M. and Oliveira, Marcel",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{Bezemer12b,
  title = "{D}eveloping {JIWY} using {TERRA}",
  author= "Bezemer, Maarten M. and Wilterdink, Robert J.W. and Broenink, Jan F.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{Miller12,
  title = "{P}olyphonic {P}rocessors - {F}antasy on an {FPGA}",
  author= "Miller, Richard",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{East12,
  title = "{A} {CPA} {S}eries",
  author= "East, Ian R.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{Welch12a,
  title = "{C}ancellable {S}ervers - a {P}attern for {C}uriousity",
  author= "Welch, Peter H.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "--",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
}
@InProceedings{Whitehead12,
  title = "{D}esigning a {C}oncurrent {F}ile {S}erver",
  author= "Whitehead, James",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "1--14",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "In this paper we present a design and architecture for a
     concurrent file system server. This architecture is a
     compromise between the fully concurrent V6 UNIX
     implementation, and the simple sequential implementation in
     the MINIX operating system. The design of the server is made
     easier through the use of a disciplined model of
     concurrency, based on the CSP process algebra. By viewing
     the problem through this restricted lens, without
     traditional explicit locking mechanisms, we can construct
     the system as a process network of components with
     explicit connections and dependencies. This provides us with
     insight into the problem domain, and allows us to analyse
     the issues present in concurrent file system implementation."
}
@InProceedings{BarrocasOliveira12a,
  title = "{JC}ircus 2.0: an {E}xtension of an {A}utomatic {T}ranslator from {C}ircus to {J}ava",
  author= "Barrocas, S.L.M. and Oliveira, Marcel",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "15--36",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "The use of formal methods in the development of concurrent
     systems considerably reduces the complexity of specifying
     their behaviour and verifying properties that are inherent
     to them. Development, however, targets the generation of
     executable programs; hence, translating the final
     specification into a practical programming language
     becomes imperative. This translation is usually rather
     problematic due to the high probability of introducing
     errors in manual translations: the mapping from some of the
     original concepts in the formal concurrency model into a
     corresponding construct in the programming language
     is non-trivial. In recent years, there is a growing effort
     in providing automatic translation from formal
     specifications into programming languages. One of these
     efforts, JCircus, translates specifications written in
     Circus (a combination of Z and CSP) into Java programs
     that use JCSP, a library that implements most of the CSP
     constructs. The subtle differences between JCSP and Circus
     implementation of concurrency, however, imposed restrictions
     to the translation strategy and, consequently, to JCircus.
     In this paper, we extend JCircus by providing: (1) a new
     optimised translation strategy to multi-way synchronisation;
     (2) the translation of complex communications, and; (3) the
     translation of CSP sharing parallel and interleaving. A
     performance analysis of the resulting code is also in the
     context of this paper and provides important insights into
     the practical use of our results."
}
@InProceedings{KosekGehrke12,
  title = "{A} {D}istributed {M}ulti-{A}gent {C}ontrol {S}ystem for {P}ower {C}onsumption in {B}uildings",
  author= "Kosek, Anna and Gehrke, Oliver",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "37--52",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "This paper presents a distributed controller for adjusting
     the electrical consumption of a residential building in
     response to an external power setpoint in Watts. The
     controller is based on a multi-agent system and has been
     implemented in JCSP. It is modularly built, capable of
     self-configuration and adapting to a dynamic environment.
     The paper describes the overall architecture and the
     design of the individual agents. Preliminary results from
     proof-of-concept tests on a real building are included."
}
@InProceedings{Wester12,
  title = "{S}pecification of {APERTIF} {P}olyphase {F}ilter {B}ank in {C}la{SH}",
  author= "Wester, Rinse and Sarakiotis, Dimitrios and Kooistra, Eric and Kuper, Jan",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "53--64",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "ClaSH, a functional hardware description language based on
     Haskell, has several abstraction mechanisms that allow a
     hardware designer to describe architectures in a short and
     concise way. In this paper we evaluate ClaSH on a complex
     DSP application, a Polyphase Filter Bank as it is used in
     the ASTRON APERTIF project. The Polyphase Filter Bank
     is implemented in two steps: first in Haskell as being close
     to a standard mathematical specification, then in ClaSH
     which is derived from the Haskell formulation by applying
     only minor changes. We show that the ClaSH formulation can
     be directly mapped to hardware, thus exploiting the
     parallelism and concurrency that is present in the
     original mathematical specification."
}
@InProceedings{Oguz12,
  title = "{S}chedulability {A}nalysis of {T}imed {CSP} {M}odels {U}sing the {PAT} {M}odel {C}hecker",
  author= "Oguz, Oguzcan and Broenink, Jan F. and Mader, Angelika",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "65--88",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "Timed CSP can be used to model and analyse real-time and
     concurrent behaviour of embedded control systems. Practical
     CSP implementations combine the CSP model of a real-time
     control system with prioritized scheduling to achieve
     efficient and orderly use of limited
     resources. Schedulability analysis of a timed CSP model of a
     system with respect to a scheduling scheme and a particular
     execution platform is important to ensure that the system
     design satisfies its timing requirements. In this paper, we
     propose a framework to analyse schedulability of CSP-based
     designs for non-preemptive fixed-priority
     multiprocessor scheduling. The framework is based on the PAT
     model checker and the analysis is done with dense-time model
     checking on timed CSP models. We also provide a
     schedulability analysis workflow to construct and analyse,
     using the proposed framework, a timed CSP model with
     scheduling from an initial untimed CSP model without
     scheduling. We demonstrate our schedulability analysis
     workflow on a case study of control software design for a
     mobile robot. The proposed approach provides non-pessimistic
     schedulability results."
}
@InProceedings{GardnerSolovyov12,
  title = "{S}upporting {T}imed {CSP} {O}perators in {CSP}++",
  author= "Gardner, W. B. and Solovyov, Yuriy",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "89--106",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "CSP++ is an open-source code synthesis tool consisting of a
     translator for a subset of CSPm and a C++ run-time
     framework. Version 5.0 now supports Timed CSP
     operators--timed interrupt, timed timeout, and
     timed prefix--as well as untimed variants of interrupt and
     timeout, with only 1\% additional execution and memory
     overhead, though using interrupts is more costly. We
     describe the implementation and performance of the
     new operators, illustrating their use with a robot-vacuum
     cleaner case study. The tool thus becomes more useful for
     specifying the behaviour of soft real-time systems, and
     generating a timing-enabled executable program from its
     formal model."
}
@InProceedings{Chalmers12,
  title = "{A} {C}omparison of {M}essage {P}assing {I}nterface and {C}ommunicating {P}rocess {A}rchitecture {N}etworking {C}ommunication {P}erformance",
  author= "Chalmers, Kevin",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "107--120",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "Message Passing Interface (MPI) is a popular approach to
     enable Single Process, Multiple Data (SPMD) style parallel
     computing, particularly in cluster computing environments.
     Communicating Process Architecture (CPA) Networking on the
     other hand, has been developed to enable channel
     based semantics across a communication mechanism in a
     transparent manner. However, in both cases the concept of a
     message passing infrastructure is fundamental. This paper
     compares the performance of both of these frameworks at a
     base communication level, also discussing some of
     the similarities between the two mechanisms. From the
     experiments, it can be seen that although MPI is a more
     mature technology, in many regards CPA Networking can
     perform comparably if the correct communication is used."
}
@InProceedings{Cole12a,
  title = "{B}eauty {A}nd {T}he {B}east: {E}xploiting {GPU}s {I}n {H}askell",
  author= "Cole, Alex and McEwan, Alistair A. and Mainland, Geoff",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "121--134",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "In this paper we compare a Haskell system that exploits a
     GPU back end using Obsidian against a number of other
     GPU/parallel processing systems. Our examples demonstrate
     two major results. Firstly they show that the Haskell
     system allows the applications programmer to exploit GPUs in
     a manner that eases the development of parallel code
     by abstracting from the hardware. Secondly we show that the
     performance results from generating the GPU code from
     Haskell are acceptably comparable to expert hand written GPU
     code in most cases; and permit very significant performance
     benefits over single and multi-threaded implementations
     whilst maintaining ease of development. Where our results
     differ from expert hand written GPU (CUDA) code we consider
     the reasons for this and discuss possible developments that
     may mitigate these differences. We conclude with a
     discussion of a domain specific example that benefits
     directly and significantly from these results."
}
@InProceedings{BateLowe12,
  title = "{A} {D}ebugger for {C}ommunicating {S}cala {O}bjects",
  author= "Bate, Andrew and Lowe, Gavin",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "135--154",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "This paper presents a software tool for visualising and
     reasoning about the behaviour of message-passing concurrent
     programs built with the CSO library for the Scala
     programming language. It describes the models needed to
     represent the construction of process networks and the
     runtime behaviour of the resulting program. We detail the
     manner in which information is extracted from the use of
     concurrency primitives in order to maintain these models and
     how these models are diagrammed. Our implementation of
     dynamic deadlock detection is explained. The tool
     can produce a sequence diagram of process communications,
     the communication network depicting the pairs of processes
     which share a communication channel, and the trees resulting
     from the composition of processes. Furthermore, it allows
     for behavioural specifications to be defined and then
     checked at runtime, and guarantees to detect the illegal
     usage of concurrency primitives that could otherwise lead to
     deadlock or data loss. Our implementation imposes only a
     small overhead on the program under inspection."
}
@InProceedings{Teig12,
  title = "{XCHAN}s: {N}otes on a {N}ew {C}hannel {T}ype",
  author= "Teig, Øyvind",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "155--170",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "This paper proposes a new channel type, XCHAN, for
     communicating messages between a sender and receiver.
     Sending on an XCHAN is asynchronous, with the sending
     process informed as to its success. XCHANs may be buffered,
     in which case a successful send means the message has got
     into the buffer. A successful send to an unbuffered XCHAN
     means the receiving process has the message. In either case,
     a failed send means the message has been discarded. If
     sending on an XCHAN fails, a built-in feedback channel (the
     x-channel, which has conventional channel semantics) will
     signal to the sender when the channel is ready for input
     (i.e., the next send will succeed). This x-channel may be
     used in a select or ALT by the sender side (only
     input guards are needed), so that the sender may passively
     wait for this notification whilst servicing other events.
     When the x-channel signal is taken, the sender should send
     as soon as possible -- but it is free to send something
     other than the message originally attempted (e.g.
     some freshly arrived data). The paper compares the use of
     XCHAN with the use of output guards in select/ALT
     statements. XCHAN usage should follow a design pattern,
     which is also described. Since the XCHAN never blocks, its
     use contributes towards deadlock- avoidance. The XCHAN
     offers one solution to the problem of overflow handling
     associated with a fast producer and slow consumer in message
     passing systems. The claim is that availability of XCHANs
     for channel based systems gives the designer and programmer
     another means to simplify and increase quality."
}
@InProceedings{Mir12,
  title = "{A} {H}igh {P}erformance {R}econfigurable {A}rchitecture for {F}lash {F}ile {S}ystems",
  author= "Mir, Irfan and McEwan, Alistair A. and Perrins, Neil J.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "171--184",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "NAND flash memory is widely adopted as the primary storage
     medium in embedded systems. The design of the flash
     translation layer, and exploitation of parallel I/O
     architectures, are crucial in achieving high performance
     within a flash file system. In this paper we present our new
     FPGA based flash management framework using
     reconfigurable computing that supports high performance
     flash storage systems. Our implementation is in Verilog, and
     as such enables us to design a highly concurrent system at a
     hardware level in both the flash translation layer and the
     flash controller. Results demonstrate that implementing the
     flash translation layer and flash controller directly in
     hardware, by exploiting reconfigurable computing, permits us
     to exploit a highly concurrent architecture that leads to
     fast response times and throughput in terms of read/write
     operations."
}
@InProceedings{Bezemer12a,
  title = "{D}esign and {U}se of {CSP} {M}eta-{M}odel for {E}mbedded {C}ontrol {S}oftware {D}evelopment",
  author= "Bezemer, Maarten M. and Wilterdink, Robert J.W. and Broenink, Jan F.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "185--200",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "Software that is used to control machines and robots must be
     predictable and reliable. Model-Driven Design (MDD)
     techniques are used to comply with both the technical and
     business needs. This paper introduces a CSP meta-model that
     is suitable for these MDD techniques. The
     meta-model describes the structure of CSP models that are
     designed; using this meta-model it is possible to use all
     regular CSP constructs when constructing a CSP model. The
     paper also presents a new tool suite, called TERRA, based on
     Eclipse and its frameworks. TERRA contains a graphical CSP
     model editor (using the new CSP meta-model),
     model validation tools and code generation tools. The model
     validation tools check whether the model conforms to the
     meta-model definition as well as to additional rules. Models
     without any validation problems result in proper code
     generation, otherwise the developer needs to address
     the found problems to be sure code generation will succeed.
     The code generation tools are able to generate CSPm code
     that is readable by FDR and to generate C++/LUNA code that
     is executable on embedded targets. The meta-model and the
     TERRA tool suite are tested by designing CSP models for
     several of our laboratory setups. The generated C++/LUNA
     code for the laboratory setups is able to control them as
     expected. Additionally, the paper contains an example model
     containing all supported CSP constructs to show the CSPm
     code generation results. So it can be concluded that the
     meta-model and TERRA are usable for these kind of tasks."
}
@InProceedings{LarsenVinter12,
  title = "{E}xception {H}andling and {C}heckpointing in {CSP}",
  author= "Larsen, Mads Ohm and Vinter, Brian",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "201--212",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "This paper describes work in progress. It presents a new way
     of looking at some of the basics of CSP. The primary
     contributions is exception handling and checkpointing of
     processes and the ability to roll back to a known
     checkpoint. Channels are discussed as communication
     events which is monitored by a supervisor process. The
     supervisor process is also used to formalise poison and
     retire events. Exception handling and checkpointing are
     used as means of recovering from an catastrophe.
     The supervisor process is central to checkpointing and
     recovery as well. Three different kind of exception handling
     is discussed: fail-stop, retire-like fail-stop, and check
     pointing. Fail-stop works like poison, and retire-like
     fail-stop works like retire. Checkpointing works by telling
     the supervisor process to roll back both participants in
     a communication event, to a state immediately after their
     last successful communication. Only fail-stop exceptions
     have been implemented in PyCSP to this point."
}
@InProceedings{Welch12c,
  title = "occam {O}bviously",
  author= "Welch, Peter H.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "213--214",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "This talk explains and tries to justify a range of questions
     for which its title is the answer. It reviews the history of
     occam: its underlying philosophy (Occam's Razor), its
     semantic foundation on Hoare's CSP, its principles of
     process oriented design and its development over
     almost three decades into occam-pi (which blends in the
     concurrency dynamics of Milner's pi-calculus). Also
     presented will be its urgent need for rationalisation --
     occam-pi is an experiment that has demonstrated significant
     results, but now needs time to be spent on careful
     review and implementing the conclusions of that review.
     Finally, the future is considered. In particular, how do we
     avoid the following question being final: which language had
     the most theoretically sound semantics, the most efficiently
     engineered implementation, the simplest and most pragmatic
     concurrency model for building complex systems ... and
     was mostly forgotten (even as its ideas are slowly and
     expensively and painfully being reinvented piece-by-piece,
     as they must be)?"
}
@InProceedings{Sampson12,
  title = "{P}rocess-{O}riented {B}uilding {B}locks",
  author= "Sampson, Adam T.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "215--216",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "Intel's Threading Building Blocks library provides an
     efficient, work-stealing lightweight task scheduler, along
     with a high-level task-based API for parallel programming in
     C++. This presentation shows how TBB's scheduler can be used
     (without modification) to implement blocking
     process-oriented concurrent systems, and discusses the
     advantages and disadvantages of this approach."
}
@InProceedings{EllisBarnes12,
  title = "{D}ata {E}scape {A}nalysis for {P}rocess {O}riented {S}ystems",
  author= "Ellis, Martin and Barnes, Frederick R. M.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "217--218",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "Escape analysis, the technique of discovering the boundaries
     of dynamically allocated objects, is a well explored
     technique for object-orientated languages (such as Java and
     C++) and stems from the functional programming community. It
     provides an insight into which objects interact directly
     (and indirectly) and can inform program correctness
     checking, or be used for directing optimisations
     (e.g. determining which objects can safely be allocated on a
     function-local stack). For process-oriented languages such
     as occam-pi and Google's Go, we have explored mobile escape
     analysis, that provides concise information about the
     movement of objects (mobiles) within networks
     of communicating processes. Because of the distinction
     between processes (as execution contexts) and objects
     (dynamically allocated data, channels and processes),
     combined with strict typing and aliasing rules, the analysis
     is somewhat simpler then for less strict languages.
     This analysis is only concerned with dynamically allocated
     blocks of memory -- it does not give any consideration for
     the data contained within these. However, knowing the extent
     to which data (statically or dynamically allocated) escapes
     within a network of communicating processes is arguably
     useful -- and is not necessarily a superset of mobile
     escape. The fringe presentation describes an extension to
     the mobile escape model that seeks to capture semantic
     information about the data escape of a process-oriented
     system. This provides richer semantic information about a
     process's behaviour (that can be used in verification) and
     has clear application to security (e.g. by demonstrating
     that particular data does not escape a set of communicating
     processes)."
}
@InProceedings{PerrinsMcEwan12,
  title = "{SEU} {P}rotection for {H}igh-{R}eliability {F}lash {F}ile {S}ystems",
  author= "Perrins, Neil J. and McEwan, Alistair A.",
  editor= "Welch, Peter H. and Barnes, Frederick R. M. and Chalmers, Kevin and Pedersen, Jan Bækgaard and Sampson, Adam T.",
  pages = "219--220",
  booktitle= "{C}ommunicating {P}rocess {A}rchitectures 2012",
  isbn= "978-0-9565409-5-9",
  year= "2012",
  month= "aug",
  abstract= "Single Event Upsets (SEU) are a primary reliability concern
     for electronics in high radiation, highly hostile
     environments such as space. In the case of Field
     Programmable Gate Arrays, the concern is firstly that data
     stored in RAM can be corrupted, and secondly
     that configurable logic blocks can become damaged or
     corrupted. In this talk we will present our considerations
     of this problem in the context of an SRAM-based high
     reliability flash file system. We will firstly demonstrate
     our test harness where we simulate the injection of
     SEUs into our FPGA. We will then discuss how we propose to
     build a self repairing configuration using triple modular
     redundancy and partial dynamic reconfiguration. Finally we
     will discuss how the reliability of the system may be tested
     and measured such that it can be used with confidence in
     either data acquisition or control system applications
     in rad-hard environments."
}

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