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WoTUG - Refer Proceedings details

Refer Proceedings details

%T PAR and STARTP Take the Tanks
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%A Øyvind Teig
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X The article describes how SPoC (Southampton Portable occam
   Compiler) has been used \-\- together with hand\-written C
   \-\- in Autronica\[rs]s new GL\-100 radar\-based fluid
   gauge. The final C\-code is running on a Texas TMS320C32
   DSP. Some 2600 lines of C code have been automatically
   translated from the occam sources. SPoC\[rs]s
   non\-preemptive scheduling filled our needs with a few
   exceptions. The main problem has been aligning occam 2 and
   ANSI\-C data abstractions. A realtime system based on
   language support of high\-level concurrency abstractions (as
   opposed to separate real\-time kernel and use of library
   calls without direct language support) is soon to monitor
   worldwide charging and discharging of oil tankers.

%T Commodity High Performance Computing at Commodity Prices
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%A Simon J. Cox, Denis A. Nicole, Kenji Takeda
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X The entry price of supercomputing has traditionally been
   very high. As processing elements, operating systems, and
   switch technology become cheap commodity parts, building a
   powerful supercomputer at a fraction of the price of a
   proprietrary system becomes realistic. We have recently
   purchased, in support of both our local and national
   collaborations, a dedicated computational cluster of eight
   DEC Alpha workstations. Each node has a 500MHz AXP 21164A
   processor with 256Mb memory running Windows NT 4.0 and cost
   under 6000 pounds. They are connected by 100Mb/s switched
   ethernet. In this paper we discuss some of the issues raised
   by our choice of processor, operating system and
   interconnection network. The results we present indicate
   that the cluster is fully competitive with systems from
   major vendors for a wide range of engineering and science
   applications, and at a lower cost by at least a factor of
   three. Indeed the only current area of under\-performance
   relative to these vendors\[rs] high\-end offerings is the
   inter\-node network bandwidth and latency. We give some
   initial results indicating how the network performance might
   be improved under Windows NT.

%T An A/D D/A board using IEEE\-1355 DS\-Links for Heterogeneous Multiprocessor Environment
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%A O. J. Greve, M. H. Schwirtz, Gerald H. Hilderink, Jan F. Broenink, André W. P. Bakkers
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X In our approach for developing heterogeneous control
   systems, we have developed a real\-time A/D D/A board called
   "the Raptor". The Raptor communicates over
   high\-speed and highly\-reliable DS\-links (IEEE\-1355). To
   obtain highly accurate analogue conversions, the A/D and D/A
   converteds have a 12\-bit resolution. We measured a maximum
   sampling frequency of 90.5kHz on each A/D channel. The
   maximum sampling frequency of each D/A channel has been
   measured to be approximately 145kHz. For communication with
   the rest of the control environment, two 100Mbit/s DS\-links
   are available. A data transfer rate of 5.57Mbytes/s has been
   achieved on each DS\-link adapter. The Raptor forms a part
   of a heterogeneous multiprocessor closed\-loop control
   environment. This new environment can be used, amongst
   others, for controlling heavy robot applications. The work
   on this environment takes place in scope of JavaPP (Java
   Plug and Play) project. The software will be developed
   together with the CJT\-library that provides inherent
   object\-orientated and parallel design patterns, according
   to CSP paradigm, in Java.

%T A Distributed Parallel Processing System for the StrongARM Microprocessor
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%A Brian C. O'Neill, G. C. Coulson, Adam K. L. Wong, R. Hotchkiss, J. H. Ng, S. Clark, P. D. Thomas, A. Cawley
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X Recent developments in hardware message routing devices have
   demonstrated significant performance benefits for parallel
   processing networks. This work describes a system which uses
   a single chip interface between the high performance
   StrongARM processor and the existing ICR C416 message
   routing chip. The ICR C416 is a non\-blocking communications
   routing device. Each device allows concurrent communications
   with up to 16 processors. A distributed parallel processing
   system can be constructed using the StrongARM and ICRC416
   devices, with features similar to that of a transputer
   system but with the benefits of the higher clock speed and
   cache memory of the StrongARM processor.

%T A PCI\-based Network Interface Controller for IEEE 1355 DS\-Links
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%A Marcel Boosten, R. W. Dobinson, B. Martin, P. D. V. van der Stok
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X We have investigated the construction of a parallel computer
   using IEEE 1355 high\-throughput low\-latency DS link
   networks and high\-performance commodity processors running
   a standard operating system. In this context a DS Network
   Interface Controller (DSNIC) has been developed. The
   board\[rs]s hardware, controlled by FPGA firmware, together
   with the host software, provides a CSP based message passing
   interface between standard OS processes. This paper
   describes how the design and realisation of the DSNIC
   refleat our aim: low\-latency high\-throughput
   inter\-process communication. We show the benchmark results,
   their analysis, and suggest further performance gains that
   might be possible.

%T IEEE 1355 DS\-Links: Present Status and Future Prospects
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%A C. R. Anderson, Marcel Boosten, R. W. Dobinson, S. Haas, R. Heeley, N. A. H. Madsen, B. Martin, J. Pech, D. A. Thornley, C. L. Ullod
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X IEEE 1355 HS\-Links and their support devices have been
   investigated as part of the ESPRIT projects Macram\[`e] and
   Arches. A description of the HS\-Link technology and initial
   experience with the RCube 8\-way packet router and the
   Bullit HS\-Link interface device are presented. A 64 node
   HS\-Link switching network based using these devices is
   being constructed at CERN. We report on the design and
   construction of the network testbed.

%T Advanced Silicon Prototyping in a Reconfigurable Environment
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%A Matt Aubury, Ian Page, Dominic Plunkett, Matthias Sauer, Jonathan Saul
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X A flow is proposed which offers a programming approach to
   the systems design of application specific
   micro\-controllers. This flow is based on Handel\-C, an
   occam\-based language with C\-like syntax for hardware
   compilation. Tools have been developed for compilation and
   concurrent simulation (co\-simulation) of hardware and
   software parts of a system, and a reconfigurable board has
   been designed which can be used for rapid prototyping of the
   application specific micro\-controller. The final design can
   be compiled into a structural VHDL netlist for a standard
   cell ASIC process.

%T A Technique for Checking the CSP sat Property
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%A Jeremy M. R. Martin, S. A. Jassim
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X This paper presents an algorithm for checking that a CSP
   process satisfies a specification defined by a
   boolean\-valued function on its traces and refusals, i.e. P
   sat f(tr, ref) This is contrasted with the refinement
   approach, as implemented by the FDR tool, of checking that
   one CSP process is a possible implementation of another,
   i.e. P >= SPEC

%T Extending CSP
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%A Adrian E. Lawrence
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X CSP, timed or untimed, has not included a general treatment
   of priority, although the PRI ALT constructor is an
   essential part of occam. This paper introduces CSPP which
   includes a generalization of PRI ALT in the form of a
   prioritized external choice P <pribox> Q. PRI
   PAR is also included. A new denotational semantics is
   introduced, although only the simplest model is outlined.
   The work is intended to provide a solid rogorous foundation
   for hardware\-software codesign. And a companion paper
   describes untimed HCSP which is a further extension of CSP
   built upon these foundations. It was first presented
   informally at the Twente WoTUG\-20 technical meeting.

%T HCSP: Extending CSP for Codesign and Shared Memory
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%A Adrian E. Lawrence
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X HCSP is a variant of CSP adapted to capture the semantics of
   hardware compilation, among other purposes. It extends CSP
   in several ways; it includes priority; events can be
   combined; new synchronization constructors are introduced;
   and state is explicitly modelled. Including state permits
   the treatment of shared memory as well as message passing
   systems. A possible denotational semantics is included here
   ths allowing proper treatment of such systems. Although most
   of these extensions were motivated by the needs of hardware
   compilation, HCSP can be applied more widely including
   software and thus can form the foundation of a codesign
   language. HCSP is an extension of CSPP; familiarity of CSPP
   is assumed here.

%T Developing an optimising compiler for occam
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%A Spiridon Kalogeropoulos
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X occam is a high\-level language which got constructs for
   generating explicitly concurrent processes which communicate
   using channels. In this paper we present our methodology for
   developing an optimising occam compiler which consist of a
   framework to represent concurrency and the semantic
   properties of an occam program that enables efficient
   process optimisations, and inter\-procedural optimisations
   to be performed. Furthermore, we tackle the issue of
   retargeting the optimising occam compiler for different
   processors of the transputer family.

%T oc\-X: an Optimising Multiprocessor occam System for the PowerPC
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%A Tim Sheen, Alastair R. Allen, Andreas Ripke, Stacy Woo
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X The development of a PowerPC port of the KRoC (portable
   occam compiler) is described. As well as the basic port, a
   multiprocessor run time system provides services for user
   programs, including efficient occam channels between
   distributed processes, natural access to host file systems
   and TCP/IP network sockets. Optimization of target assembly
   code is discussed, with methods for removing the
   inefficiencies introduced by the KRoC translation process.

%T Extended Transputer Code \-\- a Target\-Independent Representation of Parallel Programs
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%A Michael D. Poole
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X The transputer instruction set and its symbolic
   representation are reviewed. An alternative representation
   named ETC\-code, suitable for an intermediate representation
   in a retargettable occam compiler, is motivated and
   described. The translation of such a language into a variety
   of alternative target languages is discussed. Its use as a
   representation for programs whose target processor type is
   not yet known is proposed.

%T MALT: A Multiway Alternation Construct for occam
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%A Adam K. L. Wong, Francis C. M. Lau
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X The alternation construct in occam provides a form of binary
   selective communication to the cooperating tasks of a
   concurrent computation. The use of this construct could lead
   to increased responsiveness and efficiency of concurrent
   programs. However, the expressiveness of the construct is
   restricted in the sense that only two parties can be
   involved in a communication. We extend the current
   implementation of the alternation construct to accept an
   arbitrary number of channel inputs such that multiway (as
   opposed to binary) selective communication is made possible.
   A new construct called multiway alternation \-\-
   "MALT", is proposed for occam and is
   implemented in the transputer hardware.

%T Parallel Graph Colouring using Java
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%A Thomas Umland
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X In this paper a parallel, pipeline orientated version of a
   well\-known sequential graph coloring heuristic is
   introduced. Runtime and speedup results of an implementation
   in JAVA on a four processor machine are presented and
   discussed.

%T A Fault\-Tolerant On\-board Computer for Space Applications
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%A Helano de Sousa Castro, João Reinaldo Imbiriba Jr, Jarbas Aryel N. Silveira, Valdivino Santiago, Antônio Miguel Vieira Monteiro
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X The first Brazilian microsatellite will be launched at the
   middle of 1998. The on\-board computer, named Trisputer,
   will play a major part in the mission, since it will perform
   essential on\-board functions, such, as guidance, control of
   the on\-board instrumentation, telemetry/telecommand, and
   control of some on\-board scientific experiments. The
   Trisputer is a fault\-tolerant multiprocessor computer with
   a high reliability, when compared to such systems as TMR,
   and Duplex. This paper describes the conception and
   implementation of the hardware of this computer, as well as
   it shows its reliability model.

%T Design and Monitoring Systems for Parallel Programming
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%A Alexander J. Katalov, Vladimir J. Katalov, Vladimir K. Nikolaev
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications
%X In this paper we consider computer\-based systems for
   designing, debugging, tuning and optimising parallel
   programs. The development of such systems is complicated and
   labour\-intensive. Despite this, many interesting projects
   have been developed in the last few years, which can be
   effectively used to design and debug programs for parallel
   architectures. We analyse the current state in this area and
   the various approaches are compared.

%T Java Threads in the light of occam/CSP
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%A Peter H. Welch
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%E Peter H. Welch, André W. P. Bakkers
%B Proceedings of WoTUG\-21: Architectures, Languages and Patterns for Parallel and Distributed Applications

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