Internet Parallel Computing Archive

SGS-Thomson ST020-450 Transputer Datasheet
Last modified 16:00:00, 28 Sep 1995 - 853.16796875K - gzipped PostScript
32 bit microprocessor - 32-bit CPU; 0-40 MHz processor clock; 32 MIPS at 40MHz; fast integer/bit operations; 16K on-chip SRAM; 160Mbytes/s max bandwidth; Programmable memory interface: 4 separately configurable regions, 8/16/32-bits wide, support for mixed memory, 2 cycle external access, support for page mode DRAM; Serial communications; 4 OS-Links - 5/10/20 Mbits/s Link0, 10/20 Mbits/s Link1-3; Event channel; Vectored interrupt subsystem- Fully prioritized interrupts, 8 levels of preemption, 500 ns response time; Power management - low power operation, power down mode; Professional toolset support - ANSI C compiler and libraries, INQUEST advanced debugging tools; Technology - 0 to 40 MHz processor clock, 0.5 micron process technology, 3V operation, V outputs/bi-directionals, 5V inputs, 208 pin PQFP package; Test Access Port. 106 pages. 4M uncompressed.