Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
An efficient global convergence detection scheme for parallel algorithms on transputer network
By K. G. Kumar, A. Basu, S. Srinivas, A. Paulraj
The paper discusses a novel and efficient scheme for the detection of global convergence in parallel iterative algorithms. Convergence information is maintained as processes which execute concurrently with computations of the algorithm and exploit the asynchrony inherent in the progress of most executions of such algorithms towards global convergence. The scheme treats messages signalling convergence as having a lower priority as compared to those signalling non-convergence. It minimizes the waiting time at the end of iterations for convergence related communications. Analytical results indicate that the global convergence detection scheme proposed in this paper is faster than the methods proposed earlier [3]. The scheme is particularly suited for implementation on Transputer based parallel machines. An OCCAM implementation of the scheme on a torus of Transputers is described together with a method for experimental verification of the analytical results.
Complete record...
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