Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Fast Distributed Process Creation with the XMOS XS1 Architecture
By James Hanlon, Simon J. Hollis
The provision of mechanisms for processor allocation in current
distributed parallel programming models is very limited. This makes
difficult, or even prohibits, the expression of a large class of
programs which require a run-time assessment of their required
resources. This includes programs whose structure is irregular,
composite or unbounded. Efficient allocation of processors requires a
process creation mechanism able to initiate and terminate remote
computations quickly. This paper presents the design, demonstration and
analysis of an explicit mechanism to do this, implemented on the XMOS
XS1 architecture, as a foundation for a more dynamic scheme. It shows
that process creation can be made efficient so that it incurs only a
fractional overhead of the total runtime and that it can be combined
naturally with recursion to enable rapid distribution of computations
over a system.
Complete record...
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