Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Occam on Field Programmable Gate Arrays - Steps towards the Para-PC
By Barry M. Cook, Roger M. A. Peel
At the April 1998 WoTUG conference (WoTUG-21), it was reported that ST Microelectronics was ceasing production of most of the transputer family and its associated serial link components. The possibility of WoTUG members producing transputer-like devices to emulate many of the transputer\'s parallel processing and communication concepts was aired. The authors left this meeting with the challenge of designing and implementing their own transputer, preferably to be built in Field Programmable Gate Array (FPGA) devices rather than custom or semi-custom silicon, for ease of prototyping and for flexibility of modification and re-use.</p><p>
One year later, this paper outlines the progress that has been made. Rather than just producing processor logic using the standard logic design methods, the authors have written a compiler that translates occam into a number of output formats that can be fed to various logic implementation packages. Occam programs may, however, be joined to logic modules designed in a conventional fashion, using synchronised channels in the usual manner. In addition to the DS-Link interface that was announced by 4-Links at WoTUG-21, an OS-Link module has been designed by the authors, and both of these may provide external communication interfaces between occam-based hardware and the outside world.</p><p>
Although in their early stages, this paper illustrates several designs that show how occam may be used to specify small processors suitable for mapping onto FPGAs. It also shows how occam is an ideal fast prototyping mechanism for peripheral interfaces that connect to INMOS Links.
Complete record...
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