Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Parallel Scan Line algorithm for Hidden Surface Elimination
By Julian C. Highfield
With the general availability of general purpose parallel computers, there is a need to reconsider scan conversion algorithms with respect to their parallel implementation. This paper considers MIMD parallel implementation of two versions of the scan conversion algorithm, one the common edge table optimisation, and one not. Their suitability for parallel implementation is investigated and their relative performance in multi-processor systems is measured using polygonal scene descriptions of between 150 and 2600 polygons. Dependence upon the size of scene description is measured and results are extrapolated to larger scene descriptions. It is shown that scan conversion algorithms may be efficiently parallelised. It is also shown that the edge table optimisation, while appropriate to the single processor case, becomes useless at around twenty processors, and would actually be a disadvantage in the limiting case of one processor per scan line.
Complete record...
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