Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Verification of a Dynamic Channel Model using the SPIN Model-Checker
By Rune Møllegard Friborg, Brian Vinter
This paper presents the central elements of a new dynamic channel
leading towards a flexible CSP design suited for high-level languages.
This channel is separated into three models: a shared-memory channel, a
distributed channel and a dynamic synchronisation layer. The models are
described such that they may function as a basis for implementing a CSP
library, though many of the common features known in available CSP
libraries have been excluded from the models. The SPIN model checker has
been used to check for the presence of deadlocks, livelocks, starvation,
race conditions and correct channel communication behaviour. The three
models are separately verified for a variety of different process
configurations. This verification is performed automatically by doing an
exhaustive verification of all possible transitions using SPIN. The
joint result of the models is a single dynamic channel type which
supports both local and distributed any-to-any communication. This model
has not been verified and the large state-space may make it unsuited for
exhaustive verification using a model checker. An implementation of the
dynamic channel will be able to change the internal synchronisation
mechanisms on-the-fly, depending on the number of channel-ends connected
or their location.
Complete record...
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