Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
-
theory (programming models, process algebra, semantics, ...);
-
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
-
education (at school, undergraduate and postgraduate levels, ...);
-
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
-
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
-
for system integrity (dependability, security, safety, liveness, ...);
-
for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
A High Performance Reconfigurable Architecture for Flash File Systems
By Irfan Mir, Alistair A. McEwan, Neil J. Perrins
NAND flash memory is widely adopted as the primary storage medium in
embedded systems. The design of the flash translation layer, and
exploitation of parallel I/O architectures, are crucial in achieving
high performance within a flash file system. In this paper we present
our new FPGA based flash management framework using reconfigurable
computing that supports high performance flash storage systems. Our
implementation is in Verilog, and as such enables us to design a highly
concurrent system at a hardware level in both the flash translation
layer and the flash controller. Results demonstrate that implementing
the flash translation layer and flash controller directly in hardware,
by exploiting reconfigurable computing, permits us to exploit a highly
concurrent architecture that leads to fast response times and throughput
in terms of read/write operations.
Complete record...
|
