Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Development of a Family of Multi-Core Devices Using Hierarchical Abstraction
By Andrew Duller, Alan Gray, Daniel Towner, Jamie Iles, Gajinder Panesar, Will Robbins
picoChip has produced a range of commercially deployed multi-core devices, all of which have the same on-chip deterministic communications structure (the picoBus) but vary widely in the number and type of cores which make up the devices. Systems are developed from processes connected using unidirectional signals. Individual processes are described using standard C or assembly language and are grouped together in a hierarchical description of the overall system. This paper discusses how families of chips may be developed by "hardening" structures in the hierarchy of an existing software system. Hardening is the process of replacing sets of communicating processes with an equivalent hardware accelerator, without changing the interface to that sub-system. Initial development is performed using a completely software implementation, which has advantages in terms of "time to market". When cost/power reductions are required, the proposed hardening process can be used to convert certain parts of a design into fixed hardware. These can then be included in the next generation of the device. The same tool chain is used for all devices and this means that verification of the hardware accelerator against the original system is simplified. The methodology discussed has been used to produce a family of devices which have been deployed in a wide range of wireless applications around the world.
Complete record...
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