Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
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theory (programming models, process algebra, semantics, ...);
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practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
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education (at school, undergraduate and postgraduate levels, ...);
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applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
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for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
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for system integrity (dependability, security, safety, liveness, ...);
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for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
Incremental behavioral simulations on a network of transputers
By Keith Dimond, Samir Hassan
Simulation plays an important role in the design process for modern digital and analogue systems. There are many different types of simulators capable of representing the behaviour of the system at a number of different levels of abstraction. Because of its vital importance there is an ever increasing need to enhance the performance of simulators. Enhancements can occur in many different aspects. These may be in the speed of simulation, or in the accuracy of modelling. This paper describes a relatively new enhancement that of incremental operation which has the advantage of allowing the simulator to respond very rapidly to design changes in addition to providing an enhanced rate of simulation.The simulator which is described in this paper operates at the behavioural level. This allows the designer to specify, using suitable code segments descriptions of the behaviour of the functional blocks which make up the design. This approach may be used to model a digital system at the gate level, where signal values correspond to standard logic levels. In addition this mode of simulation has the attraction of being able to model very complex blocks which might very well have inputs and outputs which are most conveniently represented by complex data structures. This simulator is able therefore to model a complete system, some parts represented at this nigh-level of abstraction whilst other parts may be modelled at the lower levels of abstraction where greater detail is required.
Complete record...
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