Annual Conference: Communicating Process Architectures
Communicating Process Architectures 2018,
the 40th. WoTUG conference on concurrent and parallel systems, takes place from
Sunday August 19th. to Wednesday August 22nd. 2018 and is hosted by
Professor Dr. Rainer Spallek,
Chair of
VLSI Design, Diagnostics and Architecture
at the Faculty of Computer Science,
Technische Universität Dresden, Germany.
The conference is organised by Dr. Spallek in collboration with Oliver Knodel and Uwe Mielke
and in partnership with WoTUG.
About WoTUG
WoTUG provides a forum for the discussion and promotion of concurrency ideas,
tools and products in computer science.
It organises specialist workshops and annual conferences that address
key concurrency issues at all levels of software and hardware granularity.
WoTUG aims to progress the leading state of the art in:
-
theory (programming models, process algebra, semantics, ...);
-
practice (multicore processors and run-times, clusters, clouds, libraries, languages, verification, model checking, ...);
-
education (at school, undergraduate and postgraduate levels, ...);
-
applications (complex systems, modelling, supercomputing, embedded systems, robotics, games, e-commerce, ...);
and to stimulate discussion and ideas on the roles concurrency will play in the future:
-
for the next generation of scalable computer infrastructure (hard and soft) and application,
where scaling means the ability to ramp up functionality (stay in control as complexity increases)
as well as physical metrics (such as absolute performance and response times);
-
for system integrity (dependability, security, safety, liveness, ...);
-
for making things simple.
Of course, neither of the above sets of bullets are exclusive.
WoTUG publications
A database of papers and presentations from WoTUG conferences is here.
The Abstract below has been randomly selected from this database.
A Transputer-based Workstation Accelerator for Optimisation Algorithms
By F. W. D. Woodhams, W. L. Price
This paper discusses the design of a transputer-based accelerator for both combinatorial and global optimisation algorithms. Combinatorial optimisation has engineering applications in, for example, placement and routing of VLSI circuits. This type of problem is known to be in the complexity class NP-complete 1. For the solution of these problems some form of random search heuristic is often required. One such heuristic is the simulated annealing algorithm^. This algorithm is usually too slow for the interactive user and is normally run on a mainframe computer.
Complete record...
|
